Let have an example of most fundamental device, an AND gate. Figure 1 shows the schematic symbol for a two-input AND gate. The gate has two inputs, A and B, and a single output Y. The device computes the logical AND of A and B and puts the result on Y.
Our mission is to prove that our design, the AND gate, works correctly. To verify that it does indeed perform the AND function correctly, we first need to list the questions. The truth table helps us create the set of questions we need to verify the design. Each row of the table contains an input for A and B and the expected output for Y. Since the table is exhaustive, our generator question is, for each row in the truth table, when we apply the values of A and B identified in that row, does the device produce the expected output for Y? To answer the are-we-done question, we determine whether we have exercised each row in the truth table and received a yes answer to the does-it- work question for that row. Our are-we-done question is Do all rows work?
To automate answering both the does-it-work and are-we-done questions, we need some paraphernalia, including the following:
· A model that represents the DUT (in this case, the AND gate)
· The design intent in a form we can codify as a reference model
· Some stimuli to exercise the design
· A way to compare the result to the design intent
While our little testbench is simple, it contains key elements found in most testbenches at any level of complexity. The key elements are the following:
· DUT
· Stimulus generator—generates a sequence of stimuli for the DUT
· Scoreboard—embodies the reference model
DUT circuit
The DUT is our two-input AND gate. We implement the AND gate as a module with two inputs, A and B, and one output Y.
module and2 ( output bit Y, input A, B);
initial Y = A & B;
always @* Y = #1 A & B;
endmodule
Stimulus Generator
This example generates directed stimulus. Each new value emitted is computed in a specific order. The purpose of the stimulus generator is to produce values as inputs to the DUT. stimulus, a two-bit quantity, contains the value to be assigned to A and B. After it is incremented in each successive iteration, the low-order bit is assigned to A, and the high-order bit is assigned to B.
module stimulus(output bit A, B);
bit [1:0] stimulus_count = 0;
always #10 {A,B} = stimulus_count++;
endmodule
Scoreboard Module
The scoreboard is responsible for answering the does-it-work question. It watches the activity on the DUT and reports whether it operated correctly.1 One important thing to notice is that the structure of the scoreboard is strikingly similar to the structure of the DUT. This makes sense when you consider that the purpose of the scoreboard is to track the activity of the DUT and determine whether the DUT is working as expected. The scoreboard pins are all inputs. The scoreboard does not cause activity on the design. It passively watches the inputs and outputs of the DUT.
module scoreboard(input bit Y, A, B);
reg Y_sb, truth_table[2][2];
initial begin
truth_table[0][0] = 0;
truth_table[0][1] = 0;
truth_table[1][0] = 0;
truth_table[1][1] = 1;
end
always @(A or B) begin
Y_sb = truth_table[A][B];
#2 $display(“@%4t - %b%b : Y_sb=%b, Y=%b (%0s)”,
$time, A, B, Y_sb, Y,
((Y_sb == Y) ? “Match” : “Mis-match”));
end
endmodule
The top-level module, shown below, is completely structural; it contains instantiations of the DUT, the scoreboard, and the stimulus generator, along with the code necessary to connect them.
module top;
wire A, B, Y;
stimulus s(A, B);
and2 a(Y, A, B);
scoreboard sb(Y, A, B);
initial #100 $finish(2);
endmodule
When we run the simulation for a few iterations, here is what we get:
# @ 22 - 01 : Y_sb=0, Y=0 (Match)
# @ 32 - 10 : Y_sb=0, Y=0 (Match)
# @ 42 - 11 : Y_sb=1, Y=1 (Match)
# @ 52 - 00 : Y_sb=0, Y=0 (Match)
# @ 62 - 01 : Y_sb=0, Y=0 (Match)
# @ 72 - 10 : Y_sb=0, Y=0 (Match)
# @ 82 - 11 : Y_sb=1, Y=1 (Match)
# @ 92 - 00 : Y_sb=0, Y=0 (Match)
Each message has two parts. The first part shows the stimulus being applied. The second part shows the result of the scoreboard check that compares the DUT’s response to the predicted response. We use a colon to separate the two parts. This simple testbench illustrates the use of a stimulus generator and a scoreboard that serves as a reference. Although the DUT is a simple AND gate, all the elements of a complete testbench are present.